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About us
Contact us

Address: Room 202, 323 Zhuodaoquan, Hongshan District, Wuhan

Postal Code: 430079

Tel: 027-87873658

Mobile: 13871503113
   QQ: 449834957
WeChat:linelayout
E-Mail:linelayout@163.com
Company website: www.LineLayout.com
 
 
Business Scope

    High-speed PCB design 

Design tools

Design capacity

 

Cadence Allegro

Pads

Protel

Maximum layer 44
High-speed, high-density PCB design 
PC motherboard and industrial control board
High-speed backplane design
Blind via holes and Buried via holes design
 
Minimum BGA pin-pith: 0.4mm 
High-speed differential signal : 10 GHz differential signal
Minimum line width and distance between lines 3MIL 
Minimum via hole size
6mil (4mil Laser drill)

Design experience

DFX to consider

DDRII 800M/DDR2G /QDR/SRAM memory interface 
 ATCA, AMC, HyperTransport 
PCI, CPCI, PCI-X, PCIE, SATA, SATA II, XAUI 

DFMDesign For Manufacture
DFA
Design For Assembly
DFT
Design For Test
DFR
Design For Reliability
DFC
Design For Cost

  EMC Design and Rectification
1. Provide the specific design scheme in parts slection, power filter design, interface filter design and the like, and ensure the clients to completely consider the problems on elcctmmagnelic compatibility in the schematic diagram, so as to lay a foundation for the final products to pass the corresponding EMC certification.
 
2. Provide the relative design of stratification, layout, wiring, via hole, device placing in the PCB design. Meanwhile, focus on the consideration of the design of elcctmmagnelic compatibility in the PCB phase, as well as the consideration of the problems on EMI and relative reliability of immunity to interference from the PCB phase, in order to lower the cost of porducts.
 
  SI Simulation
1. DDR2/DDR3 SDRAM simulation analysis.
2. SI analytical report for single board, and simulation analysis and testing before and after single board.
 
  PCB design training
1.Cadence Allegro PCB design training

 

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